The present invention relates generally to data detection methods and apparatus for generalized partial-response channels in a direct access storage device, and more particularly, relates to a general methodology and apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals using transformed metrics, such as the partial matched filter branch metrics and the matched filter branch metrics and including two-way add/compare/select for improved channel speed.
Partial-response signaling with maximum-likelihood sequence detection techniques are known for digital data communication and recording applications. U.S. Pat. No. 5,619,539 discloses data detection methods and apparatus for a direct access storage device including an 8-state extended partial-response class 4 (EPR4) trellis with modified branch metrics based upon heuristics so that the number of nonzero trellis branch constants is reduced.
U.S. Pat. No. 5,430,744 discloses a Viterbi decoder having a recursive processor modified to process each node in a trellis of a partial-response coded signal via heuristics to shift the branch metric additions over the node to effectuate compare, select, add operation order on the predecessor survivor metrics terminating in that node, to compare the metrics of the predecessor sequences terminating in the node, to select a survivor sequence, and to add the shifted branch metrics to the metric of the selected survivor sequence.
A need exists for a methodology for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial-response signals. It is desirable to provide a general methodology and apparatus for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals using partial matched filter branch metrics and matched filter branch metrics.
A principal object of the present invention is to provide a methodology for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. Other important objects of the present invention are to provide Viterbi detectors for generalized partial response signals including two-way add/compare/select for improved channel speed substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value.
In accordance with features of the invention, the second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow. The two-way compare for comparing first and second state metric input values can include a hard shift for providing an add for the first state metric input value and then a compare between a resultant first state metric input value and the second state metric input value.